1. Field of the Invention
The present invention relates to an image processing device for layered graphics and a semiconductor chip implementing that device. More particularly, the present invention relates to an image processing device, as well as to a semiconductor integrated circuit chip, which reads out a plurality of source images from a graphics memory and combines them in a predetermined order to form a single picture.
2. Description of the Related Art
Graphics functions employed in some electronic devices, such as car navigation systems, take advantages of a multiple-layer structure of graphics data, where a picture is represented as a set of overlaid images that are each rendered on separate virtual drawing sheets, or layers. With the layered graphics, one can modify a particular graphical element in a picture by replacing the corresponding layer with another one. A new element can be added to an existing picture by inserting a new layer.
FIG. 12 shows a typical configuration of electronic equipment having conventional graphics display functions. As can be seen, the illustrated equipment is composed of the following elements: a host central processing unit (host CPU) 100, a read only memory (ROM) 101, a random access memory (RAM) 102, input devices 103, a graphics chip 104, a graphics memory 105, a host CPU bus 106, and a monitor unit 107. The host CPU 100 performs various operations according to the programs stored in the ROM 101 or RAM 102, besides controlling other part of the equipment. The ROM 101 stores basic programs and data that the host CPU 100 executes and manipulates. The RAM 102 serves as temporary storage for application programs and scratchpad data that the host CPU 100 executes and manipulates at runtime. The input devices 103 include a pointing device that generates signals representing user operations.
The graphics chip 104 produces each layer image according to drawing commands issued by the host CPU 100, and combines those images into a single picture for display on the monitor unit 107. The graphics memory 105 stores those images and feeds them back to graphics chip 104 when so requested. The host CPU bus 106 interconnects the host CPU 100, ROM 101, RAM 102, input devices 103, and graphics chip 104, allowing them to exchange information with each other. The monitor unit 107 is a display device such as a liquid crystal display (LCD) to show text and graphic images according to video signals supplied from the graphics chip 104.
FIG. 13 gives details of the graphics chip 104 used in the electronic equipment of FIG. 12. The graphics chip 104 contains the following functional blocks: a video timing generator 10, memory read units 11a to 11d, transparent color registers (TCR) 12a to 12d, transparent color discriminators (TCD) 13a to 13d, coefficient registers 14a to 14d, image combiners 15a to 15d, a background color register 16, a host access controller 17, and a graphics memory interface 18.
The video timing generator 10 produces a vertical synchronization signal, horizontal synchronization signal, and other necessary signals. The host CPU 100 specifies the pulse width and cycle period of those synchronization signals by sending parameters over the host CPU bus 106. Four memory read units 11a to 11d read out image data of each layer from the graphics memory 105 in burst transfer mode via the graphics memory interface 18. They also serve as buffer storage in delivering image data to its destination, outputting the contents at a signal rate that is suitable for the display device used.
The transparent color registers 12a to 12d define which color code in a picture will be interpreted as a “transparent color.” The host CPU 100 sets these registers via the host CPU bus 106. The transparent color discriminators 13a to 13d compare each pixel of incoming image data with the color code stored in the corresponding transparent color register. If a match is found, that pixel should be regarded as transparent. The image combiners 15a to 15d are informed of this transparency test result in an extended bit of image data.
The coefficient registers 14a to 14d have a width of, for example, eight bits to hold “blending coefficients” given by the host CPU 100 via the host CPU bus 106. Those blending coefficients, along with the transparency test results, are supplied to the image combiners 15a to 15d in other extended bits of image data.
Each image combiner 15a to 15d combines a source image supplied from its corresponding memory read unit 11a to 11d with a lower-layer combined image produced by the preceding image combiner. They have two operation modes: “transparent color mode” and “blend mode.” In transparent color mode, the image combiners 15a to 15d select either a given source image sent from their corresponding memory read units 11a to 11d or the combined image of lower layers, depending on the transparency test result about each pixel of the source image. Accordingly, when a layer image has a transparent region, the image combiners 15a to 15d pass lower-layer pixels to the next layer, allowing lower layers to be seen through upper layers of the picture. In blend mode, on the other hand, two images are added with certain weighting factors that are defined as the blending coefficients mentioned above.
Other circuits in the graphics chip 104 function as follows. The background color register 16 stores a color code that represents the color of a background plane. The host access controller 17 aids the host CPU 100 to make access to the graphics memory 105. Through this host access controller 17, the host CPU 100 supplies rendered image data for display. The graphics memory interface 18 is responsible for arbitration of access requests to the graphics memory 105, which are issued from the memory read units 11a to 11d and host access controller 17. It controls actual memory read/write cycles, accepting one request at a time.
With the above arrangement, the conventional graphics chip 104 operates as follows. Suppose here that a set of layered images are stored in areas A to D of the graphics memory 105 to produce a combined picture in transparent color mode. Transparent areas of each layer image are encoded with a special color code, while other opaque areas have ordinary color code values in their pixels.
The fourth memory read unit 11d for the bottom-most layer is set up with the start address of area D in the graphics memory 105. When its access request is granted by the graphics memory interface 18, the fourth memory read unit 11d reads out a predetermined amount of image data from area D, stores the data in its internal buffer (e.g., FIFO buffer), and outputs it to the corresponding image combiner 15d as requested. This data is also supplied to the transparent color discriminator 13d, which compares each incoming pixel with the code stored in the transparent color register 12d. If they match each other, the transparent color discriminator 13d records it in an extension bit of that pixel.
The fourth image combiner 15d combines the output of the background color register 16 with the image data supplied from the fourth memory read unit 11d. More specifically, the fourth image combiner 15d selects the background color code for picture areas that the transparent color discriminator 13d has determined to be transparent, while it selects the output of the fourth memory read unit 11d for the remaining areas. In this way, the graphics chip 104 combines the given area-D image with a background plane in transparent color mode.
The next memory read unit 11c, set up with the start address of area C, reads out a predetermined amount of image data from the area C when its access request is granted by the graphics memory interface 18. The third memory read unit 11c stores the data in its integral buffer for use in the corresponding image combiner 15c. The transparent color discriminator 13c compares each pixel supplied from the memory read unit 11c with a code stored in the transparent color register 12c. If they match each other, the transparent color discriminator 13c records it in an extended bit of that pixel. The third image combiner 15c chooses the output of the preceding image combiner 15d for image segments that the transparent color discriminator 13c has found it transparent, while selecting the output of the third memory read unit 11c for the remaining segments. The two image combiners 15d and 15c have thus combined the area-D and area-C images in transparent color mode, and just in the same way, the next two image combiners 15b and 15a overlay area-B and area-A images on the outcome of the third image combiner 15c. 
The architecture described above, however, is unable to exchange one layer with another with a simple command, since it requires a memory-to-memory transfer of image data or reconfiguration of address parameters in the memory read units 11a to 11d. That is, the conventional layered graphics device architecture lacks flexibility in reordering the layers in a picture.